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DMA controller (DMA)
RM0008
10.4.2
DMA interrupt flag clear register (DMA_IFCR)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CTEIF
CHTIF
CTCIF
CGIF
CTEIF
CHTIF
CTCIF
CGIF
CTEIF
CHTIF
CTCIF
CGIF
Reserved
7
w
7
w
7
w
7
w
6
w
6
w
6
w
6
w
5
w
5
w
5
w
5
w
15
CTEIF
4
w
14
CHTIF
4
w
13
CTCIF
4
w
12
CGIF
4
w
11
CTEIF
3
w
10
CHTIF
3
w
9
CTCIF
3
w
8
CGIF
3
w
7
CTEIF
2
w
6
CHTIF
2
w
5
CTCIF
2
w
4
CGIF
2
w
3
CTEIF
1
w
2
CHTIF
1
w
1
CTCIF
1
w
0
CGIF
1
w
Bits 31:28
Reserved, always read as 0.
Bits 27, 23, 19, 15, CTEIFx: Channel x transfer error clear (x = 1 ..7)
11, 7, 3
This bit is set and cleared by software.
0: No effect
1: Clears the corresponding TEIF flag in the DMA_ISR register
Bits 26, 22, 18, 14, CHTIFx: Channel x half transfer clear (x = 1 ..7)
10, 6, 2
This bit is set and cleared by software.
0: No effect
1: Clears the corresponding HTIF flag in the DMA_ISR register
Bits 25, 21, 17, 13, CTCIFx: Channel x transfer complete clear (x = 1 ..7)
9, 5, 1
This bit is set and cleared by software.
0: No effect
1: Clears the corresponding TCIF flag in the DMA_ISR register
Bits 24, 20, 16, 12, CGIFx: Channel x global interrupt clear (x = 1 ..7)
192/995
8, 4, 0
This bit is set and cleared by software.
0: No effect
1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register
Doc ID 13902 Rev 9
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